1. Field of the Invention
The present invention is related to semiconductor devices and more particularly to high performance field effect transistors (FETs) and methods of manufacturing high performance FETs.
2. Background Description
Typical semiconductor integrated circuit (IC) design goals include high performance (circuit switching frequency) and density (transistors per unit area) at minimum circuit power. Semiconductor technology and chip manufacturing advances have continually reduced circuit feature dimensions and, correspondingly, supply voltage to pack more function in the same area. To minimize power, many ICs are made in the well-known complementary insulated gate field effect transistor (FET) technology known as CMOS.
A typical CMOS circuit drives a purely or nearly pure capacitive load and includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal. A CMOS inverter, for example, is a PFET and NFET pair that are series connected between a power supply voltage (Vdd) and ground (GND), and both gated by the same input signal. Since the pair of devices have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (modeled simply as a closed switch), the other device (the PFET) is off, not conducting (ideally modeled as a simple open switch) and, vice versa. The switch is open, i.e., the device is off, when the magnitude of the gate to source voltage (Vgs) is less than that of some threshold voltage (VT). So, ideally, an NFET is off when its Vgs is below VT, and the NFET is on and conducting current above VT. Similarly, a PFET is off when its gate voltage, Vgs, is above its VT, i.e., less negative, and on below VT.
Since NFETs and PFETs are not ideal, FETs have inherent device resistance, including parasitic resistances, which may be modeled as a resistor in series with the switch. Performance depends upon how fast the CMOS circuit can charge and discharge the capacitive load, i.e., the circuit's switching speed. Device resistances limit current supplied by a particular device and slow capacitive switching. So, how fast the circuit switches the particular load switches depends both upon device on-current (which is selected by design) and these device resistances. Thus, circuit performance is maximized by maximizing device on-current and minimizing unwanted device resistance.
Another design concern is that, as FET features have shrunk, what are collectively known as short channel effects have become pronounced, resulting in a rapid increase of static power consumption. Short channel effects have occurred, in part, from a VT reduction as the FET gate length is reduced. Such VT dependence on gate length, also known as VT roll-off, which has been mitigated by thinning the transistor gate insulator. Unfortunately, especially as FET features have shrunk, thinner gate insulator (e.g., silicon oxide (SiO2) or a high-K dielectric) has resulted in increased gate leakages or gate induced leakages (i.e., gate to channel, gate to source or drain and gate induced drain leakage (GIDL)). Therefore, for circuits with transistor gate lengths shorter than 100 nm, the circuit stand-by power has become comparable to the active power.
However, short channel effects are know to improve inversely with channel thickness. So for silicon on insulator (SOI), sub-threshold leakage and other short channel effects have been controlled and reduced by thinning the surface silicon layer, i.e., the device channel layer. Fully depleted (FD) devices have been formed in what is commonly referred to as ultra-thin SOI, where the silicon channel layer is less than 50 nm. Ultra-thin FD SOI devices operate at lower effective voltage fields and constitute the leading candidate to continue scaling gate to deep sub 40 nm and beyond. Additionally, these ultra-thin SOI layers can be doped for higher mobility, which in turn increases device current and improves circuit performance. Also, ultra-thin FD SOI devices have a steeper sub-threshold current swing with current falling off sharply as Vgs drops below VT.
Unfortunately, however, forming source/drain regions that are made from the same ultra-thin silicon layer increases external resistance and in particular contact resistance. Similar high resistance source/drain diffusion and contact problems have been encountered in bulk silicon CMOS with lightly doped drain (LDD) devices, where the source/drain regions are maintained very shallow for lower voltage operation. Silicide has been tried to reduce this external resistance but has not been problem free. Especially for these very short devices, unless the source/drain silicide is spaced away from the gate, the silicide can cause gate to channel or source/drain shorts, for example. Also, silicide can interfere/interact with high-K gate dielectric formation and vice versa.
Another approach that has been used to reduce this external resistance is to selectively thicken the surface silicon layer adjacent device gates, e.g., using selective epitaxial silicon growth, to produce raised source and drain (RSD) regions. The thicker silicon RSD regions have a larger cross-sectional area for lower resistance per unit area (sheet resistance) and so, are effective in overcoming the external resistance problem. However, thickening the silicon layer to form RSD regions has also suffered from inadequate isolation and so, has suffered from an increase in source to drain shorts.
Thus, there is a need to reduce external resistance for ultra-thin SOI devices and while minimizing device on resistance.